In a SiGe bipolar CMOS (SiGe BiCMOS) process, deep hole contact process and pseudo buried layers are used to fabricate devices with small-area and low-cost. FIG. 1 is a schematic diagram showing the structure of N-type pseudo buried layers in the prior art. As shown in FIG. 1, shallow trench isolations (STI) and an active region are formed in a silicon substrate. The shallow trench isolations, namely shallow trench field oxides, are formed through etching the silicon substrate to form shallow trenches and filing silicon oxide into the shallow trenches. Conventional N-type pseudo buried layers are constituted by phosphorus impurity regions formed at the bottom of the STIs in the silicon substrate, and the phosphorus impurity regions are formed through phosphorus ion implantation into the bottom of the shallow trenches and thermal annealing thereafter. Through the thermal annealing, the phosphorus impurity regions extend laterally and vertically into the active region and into deeper parts of the silicon substrate away from the bottom of the shallow trenches.
Conventional deep hole contacts are formed in the STIs on the top of the pseudo buried layers, and the process for forming deep hole contacts includes: forming deep holes in the STIs, depositing Ti/TiN barrier metal layers in the deep holes, and then filing tungsten into the deep holes. Therefore, in the prior art, the metal in the deep holes directly contacts with the silicon, namely the pseudo buried layers at the bottom of the shallow trenches, and it is difficult to introduce metal silicide process into the manufacturing process. Meanwhile, in the SiGe BiCMOS process in the prior art, the N-type pseudo buried layers need to have a certain horizontal and vertical diffusion to meet the performance requirements of heterojunction bipolar transistors (HBT). Therefore, phosphorus is often used as the impurity implanted for the N-type pseudo buried layers due to its property of fast lateral diffusion. As conventional N-type pseudo buried layers are implanted at the early stage of the BiCMOS process, the phosphorus impurities are activated by almost all the thermal treatments throughout the BiCMOS process, which helps to satisfy the lateral diffusion requirement of the N-type pseudo buried layers, but also leads to a too low impurity concentration on the surface of the N-type pseudo buried layers, and hence a too high contact resistance between the N-type pseudo buried layers and the deep hole contacts; in some cases, it even fails to form an effective ohmic contact. Furthermore, the too low impurity concentration will also increase the sheet resistance of the N-type pseudo buried layers.